`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/10/17 21:44:50
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
    input               clk,
    input               gpio_rtl_0_tri_i,       //M21
    output [4:0]        gpio_rtl_1_tri_o,       //B1,L21,N20,V20,P17

    //P17 --- LED1      ---         0X10
    //V20 --- LED0      ---         0X08
    //M20 --- SPI_CS    ---         0X04
    //L21 --- RESET     ---         0X02
    //B1  ---           ---         0X01
    
    input               uart_rtl_0_rxd,         //N4
    output              uart_rtl_0_txd,         //K1
    inout               spi_rtl_0_io0_io,       //J14 -- MISO
    inout               spi_rtl_0_io1_io,       //K13 -- MOSI
    inout               spi_rtl_0_sck_io,       //J17 -- CLOCK
    output              spi_rtl_0_ss_io,        //N22


    //test led
    output              led0,                   //V22
    output              led1,                   //U21

    //output test
    output              pulse_test_out1,
    output              pulse_test_out2,
    output              pulse_test_out3,
    output              pulse_test_out4,
    output              pulse_test_out5,
    output              pulse_test_out6,
    output              pulse_test_out7,
    //pwm ref trig
    output              pulse_10ms_pin,     //D2
    //pwm output
    output              pwm_out1,           //F1
    output              pwm_out2,           //E3

    //encoder output
    output              wave_a_out,         //G4
    output              wave_b_out          //H5
);


wire clk_50m = clk;

// --------------------------------------------------------------------------------------------------------------
//  power on reset generate
// --------------------------------------------------------------------------------------------------------------
reg       rstn;
reg [7:0] rstn_cnt;
always@(posedge clk_50m) begin
	if(rstn_cnt != 8'hAA) begin
		rstn_cnt <= rstn_cnt + 1'b1;
	end
	if(rstn_cnt <  8'h5a) rstn     <= 1'b1;
	if(rstn_cnt == 8'h5a) rstn     <= 1'b0;
	if(rstn_cnt == 8'haa) rstn     <= 1'b1;
end 

wire rst_n     = rstn;
wire Int_Reset = rstn;

wire pulse_10ms;
wire wave_10ms;
wire pulse_ms;
wire wave_1ms;
wire pulse_100us;
wire wave_100us;
wire wave_1us;

pulse_out pulse_out_inst(
    .clk_in             (clk_50m            ),  
    .rst_n              (rst_n              ),  
    .pulse_10ms         (pulse_10ms         ),//100Hz
    .wave_10ms  	    (wave_10ms          ),  
    .pulse_ms		    (pulse_ms           ),//1kHz
    .wave_ms  		    (wave_1ms           ),
    .pulse_100us	    (pulse_100us        ),//10kHz
    .wave_100us  	    (wave_100us         ), 
    .wave_1us		    (wave_1us           ),
    .pulse_test_out1    (pulse_test_out1    ),
    .pulse_test_out2    (pulse_test_out2    ),
    .pulse_test_out3    (pulse_test_out3    ),
    .pulse_test_out4    (pulse_test_out4    ),
    .pulse_test_out5    (pulse_test_out5    ),
    .pulse_test_out6    (pulse_test_out6    ),
    .pulse_test_out7    (pulse_test_out7    )

);


pwm_out pwm_out_inst(
    .clk                (clk_50m            ),
    .rst                (rst_n              ),
    .freq_div1          (bram_data3         ),
    .freq_div2          (bram_data5         ),
    .txa_hi_frq         (pwm_out1           ),
    .txa_lw_frq         (pwm_out2           ),
    .direction          (bram_data2         ),
    .wave_a_out         (wave_a_out         ),
    .wave_b_out         (wave_b_out         )

);


wire            clk_out_100M;
(* keep = "true" *) wire [31:0]     addr_b;
(* keep = "true" *) wire [31:0]     din_b;
(* keep = "true" *) wire [31:0]     dout_b;
(* keep = "true" *) wire [3:0]      we_b;
(* keep = "true" *) wire            readEnVio;
(* keep = "true" *) wire [31:0]     AddrEndValueVio;
(* keep = "true" *) wire            en_b;
(* keep = "true" *) wire [31:0]     addrbRead;
(* keep = "true" *) wire [0:0]      rdState;
(* keep = "true" *) wire [31:0]     bram_data0;
(* keep = "true" *) wire            direction0;
(* keep = "true" *) wire [31:0]     bram_data2;
(* keep = "true" *) wire [31:0]     bram_data3;
(* keep = "true" *) wire            direction1;
(* keep = "true" *) wire [31:0]     bram_data5;
(* keep = "true" *) wire [31:0]     bram_data6;
(* keep = "true" *) wire [31:0]     bram_data7;
(* keep = "true" *) wire [31:0]     bram_data8;


bram_ctl bram_ctl_int(
    .clk_bram           (clk_50m            ),
    .rstb               (rst_n              ),
    .addrb              (addr_b             ),
    .doutb              (dout_b             ),			
    .dinb               (din_b              ),
    .bram_data0         (bram_data0         ),
    .bram_data1         (bram_data1         ),
    .bram_data2         (bram_data2         ),
    .bram_data3         (bram_data3         ),
    .bram_data4         (bram_data4         ),
    .bram_data5         (bram_data5         ),
    .bram_data6         (bram_data6         ),
    .bram_data7         (bram_data7         ),
    .we                 (we_b               ),
    .addrbRead          (addrbRead          ),
    .rdState            (rdState            ),
    .readEnVio          (pulse_10ms         ),
    .AddrEndValueVio    (AddrEndValueVio    )
);


MICROBLAZE_wrapper MICROBLAZE_wrapper_int(
    .clk_in1_0          (clk_50m            ),
    .gpio_rtl_0_tri_i   (gpio_rtl_0_tri_i   ),
    .gpio_rtl_1_tri_o   (gpio_rtl_1_tri_o   ),
    .reset_rtl_0        (rst_n              ),
    .spi_rtl_0_io0_io   (spi_rtl_0_io0_io   ),
    .spi_rtl_0_io1_io   (spi_rtl_0_io1_io   ),
    .spi_rtl_0_sck_io   (spi_rtl_0_sck_io   ),
    .spi_rtl_0_ss_io    (spi_rtl_0_ss_io    ),
    .uart_rtl_0_rxd     (uart_rtl_0_rxd     ),
    .uart_rtl_0_txd     (uart_rtl_0_txd     ),
    .clk_out2_0         (clk_out_100M       ),
    // .clk_out_100M       (clk_out_100M       ),
    .BRAM_PORTB_0_addr  (addrbRead          ),
    .BRAM_PORTB_0_clk   (clk_out_100M       ),
    .BRAM_PORTB_0_din   (din_b              ),
    .BRAM_PORTB_0_dout  (dout_b             ),
    .BRAM_PORTB_0_en    (en_b               ),
    .BRAM_PORTB_0_rst   (~rst_n             ),
    .BRAM_PORTB_0_we    (we_b               ),
    .probe0_0           (readEnVio          ),
    .probe1_0           (bram_data0         ),
    .probe2_0           (direction0         ),
    .probe3_0           (bram_data2         ),
    .probe4_0           (direction1         ),
    .probe5_0           (bram_data4         ),
    .probe6_0           (bram_data5         ),
    .probe7_0           (bram_data6         ),
    .probe8_0           (bram_data7         ),
    .probe9_0           (bram_data8         ),
    .probe_out0_0       (en_b               ),
    .probe_out1_0       (AddrEndValueVio    ),
    .probe_out2_0       (readEnVio          )
    // .spi_cs             (spi_rtl_0_ss_io    ),
    // .spi_sck            (spi_rtl_0_sck_io   ),
    // .spi_io0            (spi_rtl_0_io0_io   ),
    // .spi_io1            (spi_rtl_0_io1_io   )
);



endmodule
